In a computer system, data are read, processed and transferred via a bus system as illustrated in FIG. 1, wherein a CPU (Central Processing Unit) 10, a core logic chip) 11 and a bus 12 are shown. In response to a read cycle, the data required by a bus master (not shown) is processed by the CPU 10 and transferred to the bus master via a bus controller 110 disposed in the core logic chip 11 and the bus 12. When a plurality of read cycles are asserted for reading a series of data, the data, after being processed by some types of CPU, e.g. AMD K8 processor, might be transferred to the bus 12 randomly. Therefore, a data buffer 1100 disposed in the bus controller 110 works to reorder data so that the data can be transferred to the bus 12 in order. For example, the CPU 10 processes data in response to read cycle 1, read cycle 2, read cycle 3 and read cycle 4 to obtain data 1, data 2, data 3 and data 4, respectively. However, the four data transferred to the bus 12 may be in a sequence of data 3, data 4, data 1 and data 2. For reordering the four data, all the data received earlier but sequenced later will be temporarily stored in the data buffer 1100 until the data sequenced prior thereto are transferred. In the above example, previously received data 3 and data 4 have to be stored in the data buffer 1100 until data 1 and data 2 are transferred to the bus 12. In other words, the space of the data buffer is ineffectively occupied and much of the resource is wasted.